With higher levels of integrated circuits on semiconductor chips, such as silicon, and the need for faster transistors in these circuits, the FET transistor, with its gate separated from the silicon by a gate oxide and positioned between a source and drain in the silicon, must be fabricated to either minimize or eliminate any undesirable aspects, such as parasitic edge or corner transistors at the interface of the FET region and the trench at the crossover of the gate electrode to achieve FET transistors in integrated circuits with faster switching speed and without the potential of latchup.
Higher levels of integration requires increasing numbers of transistors isolated from each other in essentially the same amount of silicon real estate as lower levels of integration. Trench isolation, in contrast to recessed oxidation isolation, commonly know as LOCOS, is the formation of thin, vertical grooves in the silicon so that the amount of silicon real estate is minimized thereby leaving more silicon for the FETs and passive devices. Trenches normally are fabricated by anisotropically etching with a plasma gas(es) to which the silicon is selective to create substantially parallel walls or an U-shape groove deep in the silicon. If desired, V-shaped grooves can be formed by preferential wet etching of the (110) crystal plane of a {100} silicon wafer. Both of these trenches are filled with an insulating material, such as an oxide or nitride of silicon or an organic insulating material like polyimide. The walls of the etched silicon can be thermally oxidized prior to filling the trench, if so desired.
Although trench isolation saves silicon for more FETs and passive devices, this isolation technique produces parasitic transistors due to the source and drain impurities of the FET at the edges of the trench and the gate electrode crossing over and being recessed in the trench. These parasitic transistors are detrimental to the integrated circuit for at least two reasons. They increase the OFF current of the FETs, and they turn on at a lower voltage than the FETs and create a "subthreshold kink" in the current-voltage (I.sub.D -V.sub.G) characteristic curve. As the FETs are designed with smaller and smaller dimensions for higher levels of integration, the applied voltage to the FET is being lowered and the detrimental influence of the parasitic edge transistor on the operation of integrated circuit becomes even greater.
In addition, if a metal silicide is used as part of the gate electrode, junction leakage or breakdown may occur if the fabrication process allows the silicide to be in close proximity with the metallurgical junctions of the source and drain. Shorting also may occur if the metal silicide extends below metallurgical junction in the trench.